Bypass control system for high-voltage dc converter using semiconductor control rectifiers

ABSTRACT

A bypass control system wherein the rectifiers or inverters in high-voltage DC power transmission, DC interconnecting frequency changer and so forth are constituted by semiconductor controlled rectifiers, and the design is made such that the semiconductor controlled rectifiers constituting two arms in series of the converter can be fired simultaneously if necessary, thereby eliminating bypass valves required for removing the conventional converter. The removal of the converter can be achieved in a short time in case that one arm has brought about commutation failure and the other arm connected in series therewith is fired.

United States Patent -Machida .et al.

[54] BYPASS CONTROL SYSTEM FOR HIGH-VOLTAGE DC CONVERTER USINGSEMICONDUCTOR CONTROL RECTIFIERS [72] Inventors: Talrehiko Machirla;Yultio Yolllida, both of Tokyo; Noriyoslil Fujil; Kenliro Yokoyama, bothof l-iitachi-shi, all of Japan [731 Assignees: Hitachi Ltd.;"ZaidanHojln Dem-yo Chuo Kenkyuslio, Tokyo, Japan [22] Filed: Dec. 24, 1969 211App]. No.: 887,934

[30] Foreign Application Priority Data Dec. 27, 1968 Japan ....43/95466Dec. 27, 1968 Japan. ..43/95468 [52] U.S. CI 1/11, 321/13 [51] Int. Cl...H02|n l/08, l-l02m 1/ 18 [58] Field of Search ..321/l1-14, 27;315/119,123, 252

[56] References Cited UNITED STATES PATENTS 2,532,108 11/1950 Lamm..321/11 f; VAL V5 VALVE [4 1 Jan. 18, 1972 Lamm ..'.....321/113,405,344 10/1968 Boksjo et a1. ..321/27 X OTHER PUBLICATIONS Adamsonand Hingorani, High-Voltage Direct Current Transmission, Garraway Ltd.,London 1960, pp. 89, 90

IEE, l-ligh- Voltage DC Transmission, Conference Publication No. 22,Part 1 contributions, Sequential Operation of HVDC Converters WithoutBy-Pass Valves" pp. 207- 210 Primary Examiner-William H. Beha, Jr.Attorney-Craig, Antonelli & Hill [57] ABSTRACT A bypass control systemwherein the rectifiers or inverters in high-voltage DC powertransmission, DC interconnecting frequency changer and so forth areconstituted by semiconductor controlled rectifiers, and the design ismade such that the semiconductor controlled rectifiers constituting twoarms in series of the converter can be fired simultaneously ifnecessary, thereby eliminating bypass valves required for removing theconventional converter. The removal of the converter can be achieved ina short time in case that one armhas brought about commutation failureand the other ann connected in series therewith is fired.

9 Claims, 10 Drawing FIR/N6 FOR V 7 1440 5 I PATENTEU M1819?! 3I638431sum 6 or 7 INVENTOR$ TAKE/(1K0 macnroa YuKIo YOSHIOAD NnRIYasHI F1471];and KENTIR: YOKOYAMA' ATTORNEYS BYPASS CONTROL SYSTEM FOR HIGH-VOLTAGEDC CONVERTER USING SEMICONDUCTOR CONTROL REC TIF IERS This inventionrelates to a bypass control system for achieving removal of a converterfor high-voltage DC transmission, DC interconnecting frequency changerand so forth.

[In the conventional DC power transmission system, for example, it iswell known that the converter is constituted by the use of mercury arcrectifiers, and this has practically been achieved. Recently, however,attempts have been made to construct such a converter by usingsemiconductor controlled rectifiers (referred to as thyristorshereinafter), as a result of the development of such improvedthyristors. As is wellknown in the art, mercury arc rectifiers aredisadvantageous in that they not only necessitate various types of an anumber of auxiliary devices but also essentially fail to avoid backfire.This inevitably leads to the complication of the control and protectionsystem and are incapability of continuous stable running. In contrast,thyristors are essentially free from such backfire, and therefore it ispossible to simplify the control and protection system and effectcontinuous stable running by the use of such thyristors.

Generally, a plurality of rectifiers or inverters are connected inseries with each other to construct the converter, whether the latteruses mercury arc rectifiers or thyristors. Hence, it is essential thatthe design be made so that the function of DC power transmission is notinterrupted due to such trouble as commutation failure for example whichoccurs with any of the rectifiers or inverters. To this end, a bypasscircuit is provided for each rectifier or inverter so that upon theoccurrence of trouble in any of the rectifiers or inverters, the currentis transferred to the bypass circuit associated therewith thereby toremove such a rectifier or inverter. In order to avoid the occurrence ofan arc in the bypass circuit, a bypass valve is provided for the purposeof previously bridging the bypass circuit, so that the current may betransferred to the bypass circuit through the valve. However, such anarrangement is economically disadvantageous because such bypass valvesare expensive.

The present invention has been made in view of the fact that thyristorsare essentially free from backfire in the case where they are used toconstruct a converter.

Accordingly, it is a primary object of the present invention to providea control system wherein it is possible to omit bypass valves fortransferring current to a bypass circuit.

Another object of the present invention is to provide a control systemwherein circuits utilizable in place of bypass valves can be establishedby making use of an arm upon commutation failure.

Still another object of the present invention is to provide a controlsystem wherein unnecessary trouble can be prevented which tends to becaused when a current is transferred from a converter to a bypasscircuit.

This invention is characterized in that the use of bypass valves can beeliminated by simultaneously firing two arms in series constituted byrectifiers or inverters, and that one of these arms may be regarded asone with commutation failure, if desired, so that a current can betransferred to a bypass circuit in a short time. A further feature ofthe present invention is such that the transfer of the currenttransferred from the two arms in series to the bypass circuit iseffected after the AC side of the rectifiers or inverters is opened,thereby preventing DC shorbcircuiting due to error arc-through which mayhave occurred in the other arms.

Other objects, features and advantages of the present invention willbecome apparent from the following description taken in conjunction withthe accompanying drawings, in which:

FIG. 1 is a block diagram showing an example of the arrangement of acommon DC power transmission facility;

FIG. 2 is a connection diagram showing an example of the unitarrangement of a converter;

FIG. 3 is a block diagram showing the main portion of an embodiment ofthe present invention;

FIGS. 4, 5 and 6 are waveforms useful for explaining the operation ofthe embodiment shown in FIG. 3, respectively;

FIG. 7 is a control flow chart useful for explaining the opening-closingcontrol for the bypass switch according to the present invention;

FIG. 8 is a view showing an example of the voltage-current detectingstation for effecting the control described above in connection withFIG. 7;

FIG. 9 is a connection diagram showing an example of the control circuitfor effecting the control described above in connection with FIG. 7; and

FIG. 10 is a waveform useful for explaining the operation of the circuitshown in FIG. 9.

Referring to FIG. 1, numerals l and 2 represent AC buses, respectively,3, 4, 5 and 6 transformers, respectively, 7, 8, 9 and 10 converters,respectively, 11 and 12 DC power transmission lines, respectively, andl3, l4, l5 and 16 DC reactors, respectively. For example, the converters7 and 8 are made to operate as rectifiers, whereas the converters 9 and10 are made to operate as inverters, so that power may be transmittedfrom the bus 1 to the bus 2. At times, however, there is such a reverseoccasion that the converters 9 and 10 are made to serve as rectifiersand the converters 7 and 8 as inverters so that power may be transmittedfrom the bus 2 to the bus 1.

Referring now to FIG. 2, brief description will be made of theconventional control for effecting the starting or stopping of such a DCpower transmission facility as described above or effecting partialstopping of the converters without interrupting the entire operation ofthe facility.

FIG. 2 is a view useful for explaining the converters 7, 8 or 9, 10 orone unit constituting such converters, wherein numeral 21 indicates anAC bus, 22 a circuit breaker, 23 a transformer, 24 a switch forconverter, Up, Vp, Wp, Un, Vn and Wn valves connected in six-phasegraetz connection for the respective arms of the transformer and each ofwhich is constituted by a mercury arc rectifier; 31 and 32 DC buses; 33a bypass valve bridging the buses 31 and 32, 34 also a bypass valve; and35 and 36 separating switches. The AC bus 21 corresponds to the bus 1 or2 in FIG. 1, and the transformer 23 to the transformer 3 or unitassociated therewith, for example.

In the case where the bypass valve 33 such as shown in the drawing isprovided in the converter, then the converter can be separated from thesystem without interrupting the entire operation of the DC powertransmission facility by gateblocking the respective valves Up, Vp, Wn,firing the bypass valve 33 to cause DC current to flow through thebypass valve 33, subsequently turning on the bypass switch 34 andfurther opening the separating switches 35 and 36. Reversely, in anattempt to render the converter operative, the separating switches 35and 36 are first turned on to fire the bypass valve 33, and the bypassswitch 34 is opened. Subsequently, the respective valves Up, Vp, Wn aregate-controlled as converters, and the bypass valve 33 isarc-extinguished. Thus the converter can be made to take part in theoperation.

i In the case where each arm of the converter is constituted by amercury arc rectifier, since it is often the case that backfire occurseven during normal operation, a bypass valve is essentially required toextinguish such backfire in order to recover normal operation.Therefore, the foregoing control system has conveniently been utilizedto facilitate the controlling operation.

However, there is essentially no possibility that backfire occurs with athyristor, and therefore in the case where use is made of a thyristor,it is essentially not needed to provide a bypass valve for the purposeof countering against backfire. In the case where each arm of theconverter is constituted by a thyristor, therefore, it is desirable thatthe bypass valve be eliminated. The present invention is intended toachieve this.

As will be seen also from the foregoing, the function of the bypassvalve 33 is only to bypass a current flowing through each arm of theconverter. Therefore, if the valves say Up and Un constituting two armsin series of the converter can be fired at the same-time, and thiscauses no trouble with respect I 3 to the equipment, then it is possibleto replace the bypass valve 33 with the series circuit (referred to as abypass pair), so that the bypass valve 33 can be omitted. However, inthe 'case where the valves are constituted by mercury arc rectifiers,there is the possibility that even when the valves Up and Un are firedat the same time, the remaining valve Up, Vn, Wp and Wu are backfired,thus resulting in the secondary side of the transformer 23 beingshort-circuited AC-wise. For this reason, the foregoing cannot beachieved. On the other hand, in the case where thyristors are used,there occurs no phenomenon of backfire, and therefore the foregoing canbe achieved by specially designing the control. Description will now bemade of the bypass control system according to the present invention.FIG. 3 is a block diagram showing an example of the main portion of thepresent invention in which for each valve, there are provided anautomatlc pulse phase shifter circuit APPS for imparting thereto afiring pulse of which the phase depends upon whether the output voltage(current) is available from the rectifier or inverter, and a firingcircuit which is constituted mainly by a pulse transformer for firingthe valves by the use of the output of the pulse phase shifter circuit,as will be readily apparent to those skilled in the art. In FIG. 3, theAPPS and firing circuits are indicated in block form at 38 and 39,respectively. In accordance with the present invention, there isprovided an additional circuit 40 in addition to the APPS and firingcircuits. This additional circuit 40 will be described below. Thenumeral 41 denotes a commutation failure detecting circuit adapted toprovide an output by detecting a commutation failure of the converter inaccordance with the relationship between the magnitudes of the phasevoltage and current. Numeral 42 indicates a bypass pair operationinstructing circuit which is adapted to provide an output in thepresence of either the output of the aforementioned commutation failuredetecting circuit 41 or bypass pair signal which is manually externallyimparted to a terminal MS. Numerals 43, 44, and 48 represent AND gatesrespectively which are adapted to provide an output when the bypass pairoperation instruction circuit 42 provides an output and the APPSassociated with each of the valves Un, Vn, Wp corresponding to the gatesprovides an output. Numerals 49, 55, and 54 indicate memory circuitsrespectively each of which may be constituted mainly by a flip-flop forexample and which are adapted to store the outputs of the correspondinggates 43, 44, and 48 when such outputs occur respectively and extinguishthe stored outputs when a reset signal is imparted to a terminal MR.Numeral 55 represents an OR circuit which is adapted to provide anoutput when an output is available from any of the memory circuits 49,50, and 54. Numeral 56 denotes a block instructing circuit which isadapted to provide an output when an output is present at the OR-circuit55. When an output is provided by the block instruction circuit 56, theAPPS associated with each valve of the converter is stopped fromoperation, so that no output is available therefrom. Numeral 57represents a pulse generating circuit which may be constituted mainly bya one-shot multivibrator and which is energized by the output of theOR-circuit 55 so as to generate a pulse which lasts for a predeterminedperiod of time with the point of time when the output of the OR circuitoccurs as the reference. Numeral 58 indicates an inhibit gate which isadapted to provide an output in the presence of the output of the pulsegenerating circuit 57 and yet in the absence of the output of thecommutation failure detecting circuit 41. Numerals 59, 60, and 64represent AND gates which are adapted to provide an output when theinhibit circuit 58 and the corresponding memory circuits 54, 49,

and 53 provide outputs. The outputs of the respective AND gates arepassed to the firing circuits associated with the corresponding valvesof the firing circuit 39.

The additional circuit 40 is constructed as above. Here, the followingshould be noted. That is, a firing input is imparted not only directlyto the firing circuits associated with the respective valves from thecorresponding APPSs but also through the additional circuit 40. As shownin the drawing,

correspondence is established with the phase shifted in such a manner asfrom the APPS of the valve Un to the firing circuit associated with thevalve Vn. Furthermore, it is only when no output is available from thecommutation failure detecting circuit 41 that the respective firingcircuits are provided with a firing input through the additional circuit40.

The operation of the circuit shown in FIG. 3 will now be described withreference to the waveforms shown in FIGS; 4, 5 and 6. FIG. 4 illustratesthe operation of the bypass pair which is performed by the use of anexternal bypass pair signal while serving as a rectifier; FIG. 5 theoperation of the bypass pair which is performed by an external bypasspair signal while serving as an inverter; and FIG. 6 the operation ofthe bypass pair which is performed as a result of detection ofcommutation failure while serving as an inverter. In FIG. 4 each of thevalves Up, Wn, Vp Vn is provided with a firing pulse at time t 2, rrespectively, from circuit APPS 38 and these valves are fired in apredetermined sequence. The valve Vp is further supplied with a bypasssignal at its terminal NS at time t immediately after the firing pulseand, as a result, an output is produced by the bypass pair operationinstructing circuit 42. When the output is produced in the instructingcircuit 42, because the gates 43, 44 48 pass the outputs from the APPS38, the output of APPS 38 which is supplied to the valve Un, on whichvalve a firing pulse is successively applied and the valve Vp, is storedin the memory circuit 40 at time r, When an output is provided by thememory circuit 49, OR-circuit 55 provides an output and, hence, a gateblock signal is provided by the block instruction circuit 56, causingthe APPS to produce no output thereafter. These outputs are shown inFIG. 4 by dotted lines. Accordingly, in this condition, valves Vp and Unare maintained in a firing state. If an output is produced in theOR-circuit 55, a pulse generating circuit 57 produces a pulse having apredetermined pulse width and this pulse is applied to the AND-gates 59,60 64, through an inhibit gate 58. Among the memory circuits 49, 50 54,since only the memory circuit 49 as shown in FIG. 4, produces an output,then at time 1 only the gate 60 permits application of the output of thepulse generating circuit 57 to the firing circuit. Thus, on theassumption that the firing circuit 58 provides a firing pulse to thevalve Vn only when the output of the circuit 57 is extinct, thencommutation from the valve Un to the valve Vn is effected so that thebypass pair consisting of the valves Vp and Vn is completed.

In this way, in accordance with the present invention, the gate isblocked in synchronism with a gate pulse by the fact that the bypasspair is instructed and, at the same time, the bypass pair is completedby imparting a firing pulse only to the next valve on the same polarityside as the valve to which the said gate pulse is applied. This can beachieved by specially designing either the pulse generating circuit 57or firing circuit.

FIG. 5 shows the condition where the bypass pair is instructedimmediately after a firing pulse has been imparted to the valve Wp ofthe converter during the operation of the latter and which is similar tothat shown in FIG. 4 except that an output is provided by the memorycircuit 50 since gateblock is caused in synchronism with the gate pulseapplied to the valve Vn. A bypass pair is established by the valves Wpand Wn.

In other words, at each time t I each of valves Wn, Vp Wp is providedwith a firing pulse and commutation occurs, respectively, from Un to Wn,Up to Vp, Vp to Wp, for example. At time when a bypass pair isinstructed by the signal MS, the APPS produces an output Vn at time Iand at the same time, the APPS is locked by the circuit 56. Since the 7production of the output Vn is stored in the memory circuit 50, a firingpulse is applied to the valve Wn when the circuit 58 provides no outputat time FIG. 6 shows the condition where commutation failure of theconverter, as the latter is operated as an inverter, has been detected,wherein there is shown, by way of example, a failure which has occurredin the commutation from the valve Vp to failed in commutation, by firingonly the valve Vn that is provided with an gate pulse immediately aftercommutation failure has been detected and, thereupon, effectinggateblock, since failure has been caused in the commutation from thevalve Vp to Wp. Thus, when commutation failure is detected as describedabove the output of the pulse generating circuit is blocked by the gate58. That is, the additional circuit 40 is so constructed as to possessonly the function of effecting a gate-block.

At times 1 t I each of the valves Vn, Up, Un is provided with a firingpulse and commutation occurs, respectively, from Un to Vn, Wp to Vp Wnto Un, for example. At time I when a firing pulse has been applied tothe valve Wp, which isto be commutated, and if the commutation of valveVp to valve Wp fails, this commutation failure is detected at time 1 andan output is produced in the detection circuit 41.

Consequently, the instruction circuit 42 provides an output.

and at the same time, when the pulse Vn is produced at time t the APPSis locked. The valve Vn is fired by a pulse Vn and a bypass pair isestablished by the valves Vp and Vn. In this case, since the output ofthe pulse generating circuit 57 is not utilized, the outputs of thememory circuits 49, 50, 54, which store on which valves the outputs ofthe APPS were applied when a commutation failure occurred, have nothingto do with the operation.

Since commutation failure can be self-restored, it is also possible thatthe design may be made so that a bypass pair is established not upondetection of a single commutation failures but only in case thatsuccessive commutation failure are detected. In this way, the bypasspair is established. At this time, since the bypass pair current exceedsthe overload limit of the valves, it is not permissible to flow the DCline current through the bypass pair for a long time. Accordingly, it isrequired that the bypass pair current be transferred to the bypassswitch subsequent to the establishment of the bypass air. p In thiscase, there is such a tendency that unnecessary confusion may be causedif the valves in the converter are used as a bypass pair independentlyof the AC circuit. More specially,

' if arc-through occurs in the arms other than the arms used as thebypass pair when the bypass switch is opened, then a DC short-circuit iscaused so that there is the possibility that the arms are destroyed andthe transformer is burnt-out. A second feature of the present inventionis to be able to prevent such unnecessary confusion. This feature ofthis invention will be described below.

Generally, the operation is performed with ,the converter switch 24 atthe AC side being normally closed. This is also true in an attempt totemporarily stop the converter from operation. Thus, if arc-through iscaused in the arm Vp for example due to abnormal operation of the gatecontrol circuit or the like when the arms Wp and Wu are controlled asbypass pair, then a DC short-circuit of the arm Vp-switch 34-arm Wn isestablished by closing the bypass switch subsequent to the firing of thebypass pair, so that there may occur the possibility that the arms Vp,Wu and transformer 23 are burnt.

That is, when some countermeasure should be taken in an attempt tocontrol the starting and stopping of the equipment and connection anddisconnection of the converter with the aid of the bypass pair insteadof the bypass valves, such a DC short-circuit as described above tendsto be caused, thus leading to serious trouble.

The present invention is further intended to prevent such trouble. Thatis, in accordance with the present invention, the aforementioned DCshort-circuiting is avoided by establishing a proper lockingrelationship between the bypass switch 34 and the converter switch 24,so that the aforementioned control by the bypass pair can be performedsafely and without failure.

One of the causes for the above-described problem is that the converterswitch 24 is normally closed. In so far as the control is effected bymeans of the bypass pair 33 and switch 34 as in the conventionalequipment, there is no possibility that the aforementioned DCshort-circuiting is caused even if the condition is ready for occurrenceof arc-through. Therefore, the switch 24 may remain normally closed, andnaturally it is only in such cases as that where the converter isoverhauled that this switch is opened.

In accordance with the present invention, in order to avoid theoccurrence of DC short-circuiting, the switch 24 is also controlled inopening and closing in relation to the switch 34 as shown in FIG. 7. Inthe cases (I) and (II) of FIG. 7, DC voltage 0 indicates that transitionto the next step is possible under the condition that DC voltage 0" hasbeen detected.

DC voltage 0" referred to above means that the DC voltage between thebuses 31 and 32 has become lower than a predetermined level, and thevoltage does not have to be exactly zero. In order to detect thiscondition, a voltage detecting means is provided between the buses 31and 32. The attachment of the condition DC voltage 0 means that the factthat the transformer has been switched from the state in which itfunctions as a bypass pair is detected in accordance with the conditionDC voltage 0, and this may be backed up with the AC current supplied tothe converter being made zero, if necessary. To this end, a currenttransformer 81 and current detector 82 may additionally be providedthereby to monitor the current. Referring to FIG. 8, there are shown thedetecting means described immediately above by dotted lines.

FIG. 9 shows an example of the control circuit for working the presentinvention, wherein S represents a contact for instruction of the case(I) in FIG. 7, T a contact for instructing the case (II), and X and Yauxiliary relays respectively, each of which is adapted to be energizedand operated when the contacts S and T are made when the other switch isin the nonoperable state. XA is an auxiliary relay for timing returnwhich is adapted to be energized when the relay X is operated. BPP is anauxiliary relay, the converter being controlled as bypass pair when thisrelay is operated. DBL is an auxiliary relay the converter beingcontrolled so as to essentially function as a converter. 89D and 89A arecontacts for indicating the states of the switches 34 and 24,respectively, 89DC, 89DT and 89AC, 89AT are coils for turning on and offthe switches 34 and 24, respectively. Numerals and 82 represent contactsresponsive to the outputs of the voltage and current detecting meansindicated at 80 and 82 in FIG. 8, respectively.

X X X,', Y,, Y Y, and BPP,, DBL are contacts associated with the relaysX, Y, BPP and DBL respectively, the contacts indicated by the symbolswith dash being normally closed and the remaining ones being normallyopen.

Referring to FIG. 10, there are shown various waveforms occurring at theportions of the control circuit during its operation. When a start hasbeen instructed, (or when the contact S is closed) at time t,, referringto FIG. 9, the relay X operates and consequently, the relay X isself-held through the contacts 89A4 and X and at the same time, causesthe relay X to operate through the contact X so as to cause the relayBPP to operate through a contact X and thus, a bypass pair is instructedto the converter. In other words, the operation of the relay BPPcorresponds to the production of an output in the bypass pair operationinstruction circuit 42. Furthermore, since a series circuit of thecontacts X and BPP is completed, due to the operation of the relays Xand BPP, the relay 89DT is energized, (at this time the switch 34 isclosed and, hence, the contact 89D1 is in its closed condition),therefore, at time t the switch 34 is opened. When the switch 34 isopened, since the contact 89D2 is closed, the relay 89AC is energized,whereby the switch 24 is closed at time t Due to the closing of theswitch 24, the contact XA of the relay XA, which as been in operation,and the contact 89A3 are connected in series and hence, the relay DBLoperates and also releases the self-holding operation of the relay X, soas to release the bypass pair at time t, and the converter shifts into anormal operation.

On the other hand, when a stop has been instructed at time 2 and acontact T is closed, then a relay Y is energized and it is self-heldthrough the contacts Y and 89D3. The closing of the relay Y causes relayBPP to operate and a bypass pair is instructed to the converter.Furthermore, since a series circuit of the contacts Y and BPP, iscompleted, the relay 89AT is energized, (at this time the switch 24 isclosed and the contact 89A2 is in its closed state), whereby the switch24 is opened at time Since the opening of the switch 24 causes contact89Al to be closed, a relay 89DC is energized and, thus, the switch 34 isclosed at time When the switch 34 is closed, the contact 89D3 is openedand thus, the relay Y is released and the BPP is also released.

The switch 34 can be closed only when the switch 24 is opened and,therefore, problems which might be caused by forming a bypass pair areprevented. In the shown example, there may occur between t;, and 1 ashort-time chance that the instructions for deblocking the bypass pairand converter are simultaneously given, but it is readily possible tocope with this by designing the gate circuit of the converter so thatpreference is given to the bypass pair.

As will be appreciated from the foregoing, in accordance with thepresent invention, a suitable interlock is provided between the switches24 and 34, whereby any possibility of occurrence of DC short-circuitingcan be eliminated even if arethrough is caused.

Although the present invention has been illustrated and described withrespect to specific embodiments, it is to be understood that the presentinvention is by no means limited to such specific embodiments. Thepresent invention can equally be applied to a converter used as DCinterconnecting apparatus. Furthermore, it is of course understood thatthe valves constituting each arm may be series and parallel connectionsof a plurality of thyristor cells.

Still furthermore, the pulse generating circuit 57 may be so designed asto generate a pulse corresponding to a predetermined gate pulse afterthe lapse of a predetermined period of time. Needless to say, it is alsopossible that the block circuit 56 may be so designed that only one ofthe outputs of APPSs which corresponds to the output of the pulsegenerating circuit 57 may be used, without circuit 57.

What is claimed is:

1. In a converter constructed in the form of a multiphase graetzconnection of silicon controlled rectifiers including a converter switchfor connecting said converter toan AC bus, and a bypass switch, theimprovement comprising means for bypassing said converter exclusive of abypass valve, wherein a bypass pair of said silicon controlledrectifiers is established instead of bypass valves including a bypasscontrol system for simultaneously firing two arms of said graetzconnection in series in one phase of said converter wherein said systemhas a means for closing said bypass switch only when said converterswitch is open.

2. In a converter constructed in the form of a multi-phase gateconnection in which respective arms are constituted by semiconductorcontrolled rectifiers serving as valve elements, a bypass control systemcomprising automatic pulse phase shifter circuits for controlling thedelay angle of the valves in the respective arms, a firing circuit forfiring each valve by the use of the output of said phase shiftercircuits, a bypass instruction circuit for providing an instruction toestablish a providing the pulse generating bypass pair by simultaneouslyfiring two arms in series in one phase, a memory circuit for memorizingthat one of said phase shifter circuits which first provides an outputwhen an output is provided by said instruction circuit, a blockinstruction circuit for interrupting the operation of said phase-shiftercircuit when an output is provided by said memory circuit, and a pulsegenerating circuit for generating a firing pulse to fire the valves at apredetermined time after an output is provided by said memory circuit,and means responsive to the generation of an instruction for said bypasspair irrespective of trouble in the converter, for imparting the outputof said pulse generating circuit to said firing circuit associated witha given arm in re ation to the phase shifter circuit memorized by saidmemory circuit, and means responsive to the generation of an instructionbased upon trouble in the converter, for preventing the output of saidpulse generating circuit from being imparted to said firing circuit.

3. A control system in accordance with claim 2, wherein said memorycircuit includes a plurality of storage flip-flops respectivelyassociated with each valve, each flip-flop being connected to the outputof an associated AND gate, a common input of which is connected to theoutput of said bypass instruction circuit and another input of which isconnected to the output of each respective automatic pulse phase shiftercircuit.

4. A control system in accordance with claim 3, further including aplurality of AND gates respectively associated with each of said firingcircuits, a common input of which is connected to said pulse generatingcircuit, and a respective input of which is connected to saidflip-flops.

5. A control system in accordance with claim 4, further including an ORgate connected to each of the outputs of said flip-flops and whoseoutput is connected to said block instructions circuit and wherein saidpulse generating circuit includes a monostable multivibrator responsiveto the output of said OR gate and an INHIBIT-AND gate connected to theoutput of said monostable multivibrator, the output of said INHIBIT- ANDgate being connected to each of said AND gates associated with saidfiring circuits.

6. A control system in accordance with claim 5, wherein said preventingmeans includes a communication failure detector connected to the INHIBITinput of said INHIBIT-AN D gate and to said bypass instruction circuit.

7. A control system in accordance with claim 2, wherein said controlsystem further includes a current detector associated with eachrespective phase line of said multiphaseconnection and further includinga control circuit, said control circuit including a first relayresponsive to a converter starting signal for closing a pair. ofcontacts associated across the voltage lines of said converter.

8. A control system in accordance with claim 7, further including asecond relay, connected in series with one of the contacts of said firstrelay and a self-holding contact associated therewith for holding saidrelay operation in response to the closure of a stopping switch.

9. A control system in accordance with claim 8, further including afirst set of relays connected in parallel across said voltage lines, afirst auxiliary relay and a second auxiliary relay, said first relayefiecting the operation of said converter in the bypass pair mode, theoperation of said second auxiliary relay being responsive to the closureof the contacts of said first relay.

, UNITED STATES PATENT OFFICE CERTIFICATE OF CORRECTION Patent No.3,636,431- Dated January 18,1972- Takehiko Machida, Yukio Yoshida,Noriyoshi Fujii and Kenjiro Yokoyama It is certified that error appearsin t he above-identified patent and that said Letters Patent are herebycorrected as shown below:

Columri 1, line 9, Zaidan I-Iojin Denryo Chuo should read .Zaidan HojinDenryoku Chuo Signed and sealed this 11th day of July 1972.

(SEAL) Attestf V v EDI/JAR D M. FLEI CHER, JR. R0 BERT GOT 'ISC HA LKAttesting Officer Commissioner of Patents FORM F'O-1050 (10-69)USCOMM-DC 60376-P69 R U.S. GOVERNMENT PRINTING OFFICE: l99 0-366-334UNITED STATES PATENT oFFIcE CERTIFICAE OF CGRRECTION latent No. 3, 636,431 Dated January 18, 1972 Takehiko Machida, Yukio Yoshida, NoriyoshiFujii and Kenji:

Yokoyarna It is certified that error appears in the above-identifiedpatent and that said Letters Patent are hereby corrected as shown below:

Column 1, line 9, Zaidan Hojin Denryo Chuo should read Zaidan HojinDenryoku Chuo Siggued and sealed this 11th day of July 1972.

(SEAL) Atte st EDL-JARD I LFLEICHERJR. ROBERT GOTTSCHALK AttescingOfficer Commissioner of Patents FORM PC4050 (10-69) USCOMM-DC 60376-P69u.s. GQVERNMENT PRINTING OFFICE: I969 o-ass-asa

1. In a converter constructed in the form of a multiphase graetzconnection of silicon controlled rectifiers including a converter switchfor connecting said converter to an AC bus, and a bypass switch, theimprovement comprising means for bypassing said converter exclusive of abypass valve, wherein a bypass pair of said silicon controlledrectifiers is established instead of bypass valves including a bypasscontrol system for simultaneously firing two arms of said graetzconnection in series in one phase of said converter wherein said systemhas a means for closing said bypass switch only when said converterswitch is open.
 2. In a converter constructed in the form of amulti-phase gate connection in which respective arms are constituted bysEmiconductor controlled rectifiers serving as valve elements, a bypasscontrol system comprising automatic pulse phase shifter circuits forcontrolling the delay angle of the valves in the respective arms, afiring circuit for firing each valve by the use of the output of saidphase shifter circuits, a bypass instruction circuit for providing aninstruction to establish a bypass pair by simultaneously firing two armsin series in one phase, a memory circuit for memorizing that one of saidphase shifter circuits which first provides an output when an output isprovided by said instruction circuit, a block instruction circuit forinterrupting the operation of said phase-shifter circuit when an outputis provided by said memory circuit, and a pulse generating circuit forgenerating a firing pulse to fire the valves at a predetermined timeafter an output is provided by said memory circuit, and means responsiveto the generation of an instruction for said bypass pair irrespective oftrouble in the converter, for imparting the output of said pulsegenerating circuit to said firing circuit associated with a given arm inrelation to the phase shifter circuit memorized by said memory circuit,and means responsive to the generation of an instruction based upontrouble in the converter, for preventing the output of said pulsegenerating circuit from being imparted to said firing circuit.
 3. Acontrol system in accordance with claim 2, wherein said memory circuitincludes a plurality of storage flip-flops respectively associated witheach valve, each flip-flop being connected to the output of anassociated AND gate, a common input of which is connected to the outputof said bypass instruction circuit and another input of which isconnected to the output of each respective automatic pulse phase shiftercircuit.
 4. A control system in accordance with claim 3, furtherincluding a plurality of AND gates respectively associated with each ofsaid firing circuits, a common input of which is connected to said pulsegenerating circuit, and a respective input of which is connected to saidflip-flops.
 5. A control system in accordance with claim 4, furtherincluding an OR gate connected to each of the outputs of said flip-flopsand whose output is connected to said block instructions circuit andwherein said pulse generating circuit includes a monostablemultivibrator responsive to the output of said OR gate and anINHIBIT-AND gate connected to the output of said monostablemultivibrator, the output of said INHIBIT-AND gate being connected toeach of said AND gates associated with said firing circuits.
 6. Acontrol system in accordance with claim 5, wherein said preventing meansincludes a communication failure detector connected to the INHIBIT inputof said INHIBIT-AND gate and to said bypass instruction circuit.
 7. Acontrol system in accordance with claim 2, wherein said control systemfurther includes a current detector associated with each respectivephase line of said multiphase connection and further including a controlcircuit, said control circuit including a first relay responsive to aconverter starting signal for closing a pair of contacts associatedacross the voltage lines of said converter.
 8. A control system inaccordance with claim 7, further including a second relay, connected inseries with one of the contacts of said first relay and a self-holdingcontact associated therewith for holding said relay operation inresponse to the closure of a stopping switch.
 9. A control system inaccordance with claim 8, further including a first set of relaysconnected in parallel across said voltage lines, a first auxiliary relayand a second auxiliary relay, said first relay effecting the operationof said converter in the bypass pair mode, the operation of said secondauxiliary relay being responsive to the closure of the contacts of saidfirst relay.